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ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 65 features ? 256k x 16 multiport video ram ? performance: ? fully asynchronous operation of random port and serial port ? compatible to full depth sam in srs mode ? 8 column block write with masking column and wpb masking along with individual byte control parameter -6h -60 -70 t rp re precharge 25ns 25ns 30ns t sca serial access time 12ns 15ns 17ns t cac access time from ce 15ns 15ns 17ns t aa column address access time 25ns 30ns 35ns t scc serial clock cycle time 12ns 18ns 20ns t rc read or write cycle time 95ns 95ns 110ns t pc fast page mode cycle time 30ns 30ns 40ns t hpc extended data out cycle time 20ns 25ns 30ns ? 50 mhz edo performance ? flash write with wpbm- 512 x 16 bits ? persistent & non-persistent wpbm mode ? split serial register with width control ? 256 location start address pointer for sam ? full read and split read transfer ? masked write transfer ? masked split write transfer ? power supply: 5.0v 0.5v and 3.3v 0.3v ? high performance, cmos 0.55 m m process ? ssog-64 jedec standard ? ttl compatible description this 4mb dual port video ram (vram) consists of a dynamic random access memory (dram) orga- nized as 256k x 16 interfaced to a serial register / serial access memory (sam) organized as 256 x 16. the vram supports three basic operations: bidirectional random access to the dram, bidirec- tional serial access to the sam, and bidirectional data transfer between any dram row and the sam. full compatibility is provided between half depth sam (256 x 16) and full depth sam (512 x 16) by setting the vram in serial register stop (srs) mode with a stop address of 128 bit (or less). unique features have been added to these basic vram operations to improve graphics performance of the system. higher update rates can be achieved with either flash write or block write modes. two w or two ce inputs are provided for individual byte con- trol for both normal write and block write. for indi- vidual bit control, a write-per-bit mask (wpbm) can be supplied on the data pins at re time to be used during masked write transfers or masked write cycles. a permanent mask to be used during block write cycles can be loaded using the load mask register (lmr) cycle. ibm025160256 x 16fp, 2ce. ibm025171256 x 16edo, 2we. ibm025170256 x 16fp, 2we. IBM025161256 x 16edo, 2ce.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 65 33g0307 sa14-4751-05 revised 3/98 pin assignments pin description sc se v ss sdq15 dq15 sdq14 dq14 v cc sdq13 dq13 sdq12 dq12 v ss sdq11 dq11 sdq10 dq10 v cc sdq9 dq9 sdq8 dq8 v ss dsf nc ce, uce nc a0 a1 a2 a3 v ss v cc trg v ss sdq0 dq0 sdq1 dq1 v cc sdq2 dq2 sdq3 dq3 v ss sdq4 dq4 sdq5 dq5 v cc sdq6 dq6 sdq7 dq7 v ss l w, lce uw, w re a8 a7 a6 a5 a4 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 re row enable ce column enable (only in dual we parts) lce, uce lower & upper column enable (only in dual ce parts) w write (only in dual ce parts) lw, uw lower & upper byte write (only in dual w parts) trg data transfer & output enable dsf designated special function a 8 -a 0 address inputs dq 15 - dq 0 random port data input/output sdq 15 - sdq 0 serial port data input/output sc serial clock se serial enable v cc voltage (5.0v 0.5v or 3.3v 0.3v). all volt- ages are referenced to the nearest v ss pin . v ss ground. v ss =0v nc no connect
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 65 detailed pin description re - row enable; also known as ras this pin is functionally equivalent to a chip enable signal in that whenever it is activated, 8192 storage cells of the selected row are sensed simultaneously and the sense amplifiers restore all data. the falling edge of re latches data on address pins a 0 -a 8 . ce, trg, w, and dsf are simultaneously latched to invoke the dram port and serial port operations. ce - column enable (dual we parts only); also known as cas. this pin serves as a chip select signal. it activates the column decoder and the i/o buffer. the falling edge of ce latches the column address a 0 -a 8 . state of dsf at falling edge of ce invokes various dram port and serial port functions. lce, uce - lower and upper column enable (dual ce parts only). these pins enable lower and upper byte respectively of the selected column for read/write. the falling edge of either lce or uce latches the column address and state of dsf to invoke various dram port and serial port functions. w - write (dual ce parts only) this pin enables the dram port write circuitry. it is also used as a control input pin to define the various oper- ations at re fall time. l w, uw - lower and upper write (only in dual w parts) these pins enable the dram port write circuitry for lower and upper byte write respectively. either lw or uw being low is considered low for write cycles. trg - data transfer and output enable ( dt/ oe) this is a multifunctional input pin. in conjunction with lw/ uw, dsf and ce, it either enables the dram data outputs or enables transfer operations between dram and sam. this is also used as a control input pin to define the various operating modes at re time. dsf - designated special function a control pin used in conjunction with other control pins to define the various operating modes at re and ce time. a 0 - a 8 - address inputs these pins are multiplexed as row and column address inputs. row addresses are first used to select one of the possible 512 rows for a read, write, data transfer, or refresh cycles. column addresses are then sup- plied to select one of the possible 512 columns for a read or a write cycle or one of the possible 256 starting locations for the next serial read/write cycle for the serial port.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 65 33g0307 sa14-4751-05 revised 3/98 dq 0 - dq 15 - random port data input/output in a read cycle, these pins serve as outputs for the selected storage cells. in a write cycle, data input on these pins is latched by the falling edge of ce or lw/ uw whichever occurs later. data will not appear at the outputs until after both ce and trg have been brought low. during transfer operations, the dq outputs remain in the high-z state for the entire cycle. in a block write cycle, data input on these pins is used to mask the selected columns in the block. at re falling edge, the data input at these pins can be used for loading the write-per-bit mask (wpbm). sdq 0 - sdq 15 - serial port data input/output 16 bit data can be written or read from these pins. the output data remains valid until the next sc clock is activated. sc - serial clock the rising edge of the sc signal is used to initiate a read/write from/to the sam register (starting from the location specified in the data transfer cycle). in the serial read mode, 16 of the 4096 data bits from the sam register are transferred to 16 serial data buses and read out. in the serial write operation, input data is latched on the rising edge of sc clock. whenever sc clock is low, the serial port is in standby. se - serial port enable this signal enables or disables the serial input/output buffer. when se is high, the output of the serial port is in tri-state. while se is held high, the serial clock is not disabled. thus, external sc pulses will incre- ment the internal serial address counter regardless of the state of se. this ungated serial clock scheme minimizes access time of serial output from se low since the serial clock input buffer and the serial address counter are not disabled by se. v cc - (5.0v 0.5v) or (3.3v 0.3v) voltage. all voltages are referenced to the nearest v ss pin. v ss - circuit ground. v ss = 0v. nc - no connect. nc implies that the pin(s) should not be grounded or connected to any other signal. these pins might be used for testing some modes at factory. consult factory before using any one of nc pins.
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 65 ordering information part number features voltage speed package notes ibm025160lg5d-60 dual ce, fast page 5.0v 60ns .472 ssog ibm025160lg5d-70 70ns ibm025170lg5d-60 dual w, fast page 60ns ibm025170lg5d-70 70ns IBM025161lg5d-6h dual ce, extended data <60ns 1 IBM025161lg5d-60 60ns IBM025161lg5d-70 70ns ibm025171lg5d-6h dual w, extended data <60ns 1 ibm025171lg5d-60 60ns ibm025171lg5d-70 70ns ibm025160ng5d-60 dual ce, fast page 3.3v 60ns ibm025160ng5d-70 70ns bm025170ng5d-60 dual w, fast page 60ns ibm025170ng5d-70 70ns IBM025161ng5d-6h dual ce, extended data <60ns 1 IBM025161ng5d-60 60ns IBM025161ng5d-70 70ns ibm025171ng5d-6h dual w, extended data <60ns 1 ibm025171ng5d-60 60ns ibm025171ng5d-70 70ns 1. the -6h means 60ns high performance parts.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 65 33g0307 sa14-4751-05 revised 3/98 block diagram 9 column address latch/buffer 9 column decoders 16 16 dram output buffers 16 dq 0 to dq 15 dram input buffers 16 color registers 16 mux 16 512 sense ampli?ers 512 refresh counter 9 a 0 to a 8 9 row address latch/buffers 9 row decoders 512 512 x 512 x 16 dram array write control logic block write control logic timing generator and control logic re ce trg w dsf sc se opt, nc flash write control logic 128 128 upper transfer gate lower transfer gate 128 128 transfer control 8 8 sam address latch/buffers sam address counter sam registers 16 16 sam input/output buffers 16 sdq 0 to sdq 15 write-per bit wm1 mask se sam decoder 8 sc
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 65 truth table mne code re ce address dq 0 - dq 1 5 function ce trg w dsf dsf re ce re ce, w cbr 0(5) x 1(4) 0 - x - x - ce before re refresh (reset) (9) cbrs 0(5) x 0(3) 1 - stop(6) point -x- ce before re refresh stop point set (2) cbrn 0(5) x 1(4) 1-x - x- ce before re refresh without mode reset (10) ror 1 1 x 0 - row(1) - x - re only refresh (11) 1 1 1 x - row(1) - x - lcr 1 1 1(4) 11 row(1) x x color load color register lmr 1 1 1(4) 1 0 row(1) x x mask load mask register (13) rw 1 1 1(4) 0 0 row column x valid data input read/write cycle (no mask) rwm 1 1 0(3) 0 0 row column wpbm (7) valid data input read/write cycle (masked) bw 1 1 1(4) 0 1 row column a 3 -a 8 x column mask block write cycle (no mask) bwm 1 1 0(3) 0 1 row column a 3 -a 8 wpbm (7) column mask block write cycle (masked) fwm 1 1 0(3) 1 x row x wpbm (7) x flash write cycle (masked) (8) rt 1 0 1(4) 0 x row tap x x full - register read transfer mwt 1 0 0(3) 0 x row tap (12) wpbm (7) x masked full - register write transfer srt 1 0 1(4) 1 x row tap x x split read transfer mswt 1 0 0(3) 1 x row tap wpbm (7) x masked split write transfer 1. row address needed only for refresh operation to the selected row. otherwise this is a dont care. 2. this cycle is used to put the chip into special modes. the address at re fall becomes the serial port stop address. cbrs cycle(s) should be performed immediately after the power up initialization cycles. 3. either w is 0. 4. both w are 1. 5. either ce is 0 on dual ce parts. 6. stop de?nes the serial port address on which shift out moves to the other half of the sam. 7. after lmr, wpbm is only changed by lmr. cbr resets the persistent mask. 8. no byte select, both bytes are written. 9. cbr mode will reset all the unknown modes at power up. it will also clear persistent write-per-bit mode. 10. cbrn mode will not clear persistent write-per-bit mode. 11. ror will not clear inadvertent modes at power up time. 12. a 0 -a 7 de?ne the tap point for the serial data input after the transfer. a 8 de?nes the particular half of the dram row in which the sam data will be transferred. 13. lmr cycle will set the persistent write-per-bit mode. the persistent write-per-bit mode is reset by cbr cycle only. 14. dq 0 - dq 15 are latched on either the ?rst wex falling edge or the falling edge of cas, whichever occurs later. legend: x = dont care; - = not applicable
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 65 33g0307 sa14-4751-05 revised 3/98 absolute maximum ratings symbo l item rating units notes 5.0 volt 3.3 volt v cc power supply voltage -1.0 to +6.0 -0.5 to +4.6 v 1 t a operating temperature 0 to +70 0 to +70 c 1 t stg storage temperature -55 to +150 -55 to +150 c 1 p d power dissipation 1.3 1.3 w 1 i out short circuit output current 50 33 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a = 0 to +70 c) symbol parameter 5.0 volt 3.3 volt units notes min. typ. max. min. typ. max. v cc supply voltage 4.5 5.0 5.5 3.0 3.3 3.6 v 1 v ih input high voltage 2.4 v cc +0.5 2.0 v cc +0.3 v 1 v il input low voltage -0.5 0.8 -0.3 0.8 v 1 1. all voltages referenced to v ss . capacitance (t a = 25 c, f= 1.0 mhz) symbol parameter min. max. units notes c i1 input capacitance (addresses) 5 pf c i2 re, ce, w, trg, dsf, sc, se 7 pf c o output capacitance (dq i , sdq i ) 7pf
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 65 output drivers driver impedance output voltage, low (max) output voltage, high (min) serial port 60 15 w i out =2.0 ma, v=0.4 i out =-1 ma, v=2.4 parallel port 45 15 w i out =2.0 ma, v=0.4 i out =-1 ma, v=2.4 ac measurement conditions port detect load parallel port output detect level 2.0v / 0.8v serial port output detect level 2.0v / 0.8v parallel port output load 1 ttl + 50 pf serial port output load 1 ttl + 30 pf
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 65 33g0307 sa14-4751-05 revised 3/98 dc electrical characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v or v cc = 5.0v 0.5v) symbol parameter 5.0 volt 3.3 volt units notes min. max. min. max. i cc1 operating current (random) average power supply operating current ( re and ce cycling, t rc =120ns for -60 and -6h, t rc =130ns for -70, sc = 0) -6h 135 135 ma 1, 2, 3, 6 -60 135 135 -70 130 130 i cc2 operating current (serial) average power supply current (t scc = 20ns for -60 and -6h, t scc = 23ns for -70) -6h 40 40 ma 1, 2, 7 -60 40 40 -70 35 35 i cc3 operating current (both port) average power supply current ( re and ce cycling, t rc =120ns & t scc = 20ns for -60 and - 6h, t rc =130ns & t scc = 23ns for -70) -6h 160 160 ma 1, 2, 3, 6, 7 -60 160 16 0 -70 150 150 i cc4 fast page mode current average power supply current, fast page mode ( re v il min., ce cycling, t pc = 40ns for -60 and -6h, t pc =45ns for -70) -6h 80 80 ma 1, 2, 4, 6, 7 -60 80 80 -70 70 70 i cc5 fast page mode current (serial) average power supply current, fast page/serial ( re v il min., ce cycling, t pc = 40ns & t scc = 20ns for -60 and -6h, t pc = 45ns & t scc = 23ns for -70) -6h 85 85 ma 1, 2, 7 -60 85 85 -70 75 75 i cc6 standby supply current power supply standby current ( re = ce = v cc , sc = 0v) 55ma i cc7 data transfer current average power supply current (t rc =120ns for -60 and -6h, t rc = 130ns for -70, sc = 0v) -6h 130 130 ma -60 130 130 -70 120 120 i cc8 data transfer current average power supply current (t scc = 20ns for -60 and -6h, t scc = 23ns for -70) -6h 140 140 ma -60 140 140 -70 130 130 i i(l) input leakage current, any input (0.0 v in (v cc + 1.0v)), all other pins not under test = 0v -10 +10 -10 10 m a i o(l) output leakage current (d out is disabled, 0.0 v out v cc (max)) -10 +10 -10 10 m a v oh output level (ttl) output h level voltage (i out = -1ma, random and serial) 2.4 2.4 v 4 v ol output level (ttl) output l level voltage (i out = +2.0ma, random and serial) 0.4 0.4 v 4 1. i cc1 , i cc2 , i cc3 , i cc4 , i cc5 , i cc7 and i cc8 depend on cycle rate. 2. i cc1 , i cc2 , i cc3 , i cc4 , i cc5 , i cc7 and i cc8 depend on output loading. speci?ed values are obtained with the output open. 3. measured with one address change per re cycle. 4. measured with one column address change per page cycle. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 6. measured with trg = v ih when ce = v il . 7. measured with se = v ih .
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 65 ac characteristics (t a = 0 to +70 c) read, write, read-modify-write and refresh. cycles (part 1 of 2) (common parameters) symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t asc column address setup time 0 0 0 ns t asr row address setup time 0 0 0 ns t ar column address hold time after re low 15 20 25 ns t cah column address hold time after ce low 6 6 8 ns 5 t cas ce pulse width 12 16k 15 16k 17 16k ns t chcl first ce to return high to last ce going low 6 6 8 ns t clch last ce going low to first ce to return high 6 6 8 ns t cp ce precharge time 6 6 8 ns t crp ce high before re low precharge 5 5 10 ns 8 t csh ce hold time 60 60 70 ns t h(sfc) dsf hold time after ce low 6 6 8 ns t h(sfr) dsf hold time after re low 6 6 8 ns t mh write mask hold time after re low 6 6 8 ns t ms data-in setup before re low 0 0 0 ns t rad re to column address delay time 11 35 11 35 13 40 ns 4 t rah row address hold time after re low 6 6 8 ns t ras re pulse width 60 100k 60 100k 70 100k ns t rc ,t wc random read or write cycle time 95 95 110 ns 1, 2 t rcd delay from re low to ce low 16 45 16 45 18 53 ns 3, 5, 9 t rp re precharge time 25 25 30 ns 1, 6, 7 t rsh re hold time 15 15 17 ns t rwh w hold time after re low 6 6 8 ns t su(sfc) dsf setup time before ce low 0 0 0 ns 1. an initial pause of 100 m s is required after power up followed by 8 ce before re refresh cycles for proper device operation 2. ac measurements assume t t = 5ns. 3. operation within the t rcd (max) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?ed as a reference point only: if t rcd is greater than the speci?ed t rcd (max) limit, then access time is controlled by t cac . 4. operation within the t rad (max) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa . 5. t rcd and t cah cannot be at minimum values simultaneously. t rcd + t cah 3 45ns (60ns t rac product), t rcd + t cah 3 50ns (70ns t rac product). 6. t rwl and t rp cannot be at minimum values simultaneously. t rw l + t rp 3 60ns (60ns t rac product), t rwl + t rp 3 70ns (70ns t rac product). 7. t cwl and t rp cannot be at minimum values simultaneously. t cwl + t rp 3 60ns (60ns t rac product), t cwl + t rp 3 70ns (70ns t rac product). 8. t crp must be 15ns (60ns t rac ) or 17ns (70ns t rac ) if a write-per-bit mask is used on the following re cycle due to the fact that t off must be met. 9. during serial port write transfer t rcd (max) = 100ns.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 65 33g0307 sa14-4751-05 revised 3/98 t su(sfr) dsf setup time before re low 0 0 0 ns t t transition time (rise and fall) 3 50 3 50 3 50 ns t tlh trg hold time after re low 6 6 8 ns t tls trg setup time before re low 0 0 0 ns t wsr write setup time before re low 0 0 0 ns t wcr write hold time after re low 20 20 25 ns read, write, read-modify-write and refresh. cycles (part 2 of 2) (common parameters) symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. 1. an initial pause of 100 m s is required after power up followed by 8 ce before re refresh cycles for proper device operation 2. ac measurements assume t t = 5ns. 3. operation within the t rcd (max) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?ed as a reference point only: if t rcd is greater than the speci?ed t rcd (max) limit, then access time is controlled by t cac . 4. operation within the t rad (max) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa . 5. t rcd and t cah cannot be at minimum values simultaneously. t rcd + t cah 3 45ns (60ns t rac product), t rcd + t cah 3 50ns (70ns t rac product). 6. t rwl and t rp cannot be at minimum values simultaneously. t rw l + t rp 3 60ns (60ns t rac product), t rwl + t rp 3 70ns (70ns t rac product). 7. t cwl and t rp cannot be at minimum values simultaneously. t cwl + t rp 3 60ns (60ns t rac product), t cwl + t rp 3 70ns (70ns t rac product). 8. t crp must be 15ns (60ns t rac ) or 17ns (70ns t rac ) if a write-per-bit mask is used on the following re cycle due to the fact that t off must be met. 9. during serial port write transfer t rcd (max) = 100ns.
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 65 write cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t cwl write command setup before ce high 10 15 17 ns 4 t dh data-in hold time after ce or w low, whichever is later 688 ns 1 t dhr data-in hold time after re low 20 20 25 ns t dsc data-in setup before ce low 000 ns t dsw data-in setup before w low 000 ns t ghd trg high before data-in applied on primary port data pins 10 15 17 ns t rwl write setup time before re high 10 15 17 ns 3 t wch write hold time after ce low 668 ns t wcs early write command setup before ce low 000 ns 1, 2 t wp write command pulse width 668 ns 1. data-in setup and hold is measured from the later of the two timings - ce / uce / lce or w / uw / lw. 2. t rwd , t cwd , t awd and t cpw are not restrictive parameters. they are included as electrical characteristics only. if t wcs 3 t wcs (min) the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t cpw 3 t cpw (min) (fast page) mode, the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell; if neither of the above sets of conditions are satis?ed, the condition of the data out (at access time) is indeterminate. 3. t rwl and t rp cannot be at minimum values simultaneously. t rwl + t rp 3 60ns (60ns t rac product), t rwl + t rp 3 70ns (70ns t rac product). 4. t cwl and t rp cannot be at minimum values simultaneously. t cwl + t rp 3 60ns (60ns t rac product), t cwl + t rp 3 70ns (70ns t rac product) . read-modify-write cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t awd column address to w low 50 50 60 ns 1 t cwd ce low before w low 35 35 40 ns 1 t oeh output disable ( trg high) hold time from w low 15 15 17 ns t rwc read-modify-write cycle time 135 135 155 ns t rwd re low to w low 80 80 95 ns 1 1. t rwd , t cwd , t awd and t cpw are not restrictive parameters. they are included as electrical characteristics only. if t wcs 3 t wcs (min) the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t cpw 3 t cpw (min) (fast page) mode, the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell; if neither of the above sets of conditions are satis?ed, the condition of the data out (at access time) is indeterminate.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 65 33g0307 sa14-4751-05 revised 3/98 read cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t aa access time from column address 25 30 35 ns 2, 3 t cac access time from ce 15 15 17 ns 1, 2, 3 t oea access time from trg 15 15 17 ns t oes output enable setup ( trg low) before re high 10 10 10 ns t oez primary output disable from trg high 0 10 0 15 0 17 ns t off primary output disable from ce 0 10 0 15 0 17 ns 5 t rac access time from re 60 60 70 ns 1, 2, 3 t ral column address to re high 25 30 35 ns t rch read hold time after ce goes high 0 0 0 ns 4 t rcs read command setup time 0 0 0 ns t rrh read command hold time to ras high 0 0 0 ns 4 1. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 2. operation within the t rad (max.) limit ensures that t rac (max.) can be met t rad (max.) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max.) limit, then access time is controlled by t aa . 3. measured with the speci?ed current and 50 pf load for the primary port. output referenced levels: v oh = 2.0v and v ol = 0.8v. 4. either t rch or t rrh must be satis?ed for a read cycle. 5. t off (max.) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. fast page mode read-modify-write-cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t rwcp fast page mode read-modify-write cycle time 74 74 84 ns page mode cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t acp access time from ce precharge 28 35 40 ns t hpc extended data out cycle time 20 25 30 ns t pc fast page mode cycle time 30 35 40 ns
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 65 refresh cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t chr ce held low after re low ( ce before re refresh) 668 ns t csr ce low setup before re low ( ce before re refresh) 555 ns t ref refresh period 32 32 32 ms t rpc re high to ce low precharge 0 00 ns
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 65 33g0307 sa14-4751-05 revised 3/98 serial read, write and transfer cycle symbol parameter -6h -60 -70 units notes min. max. min. max. min. max. t csd ce low to first sc high after trg goes high 15 15 17 ns t cth delay time from ce low to trg high 15 15 15 ns t d(rhms) delay time, re high to last (most significant rising edge of sc before boundary switch during split read transfer cycles 20 20 20 ns t dth trg hold after re high 5 55ns t d(tprl) delay time, first (tap) rising edge of sc after bound- ary switch to re low during split read transfer cycles 15 15 17 ns t esr se setup before re low 000ns t rsd re low to first sc high after trg goes high 60 60 70 ns t rth re low to trg high 45 45 55 ns t sc width of sc high 4 67ns t sca access time from sc going high 3 12 3 15 3 17 ns 1 t scc serial clock cycle time 12 18 20 ns t scp width of sc low 4 67ns t sdh serial data-in hold time after sc high 5 55ns t sds serial data-in setup time to sc high 2 22ns t sea access time from se going low 10 12 15 ns t sfd serial enable setup time to sc high 3 33ns t sez serial output disable from se high 0 8 0 8 0 10 ns t soh old serial data out hold time after sc high 3 33ns t srs sc going high to re low 8 8 10 ns t sws trg high to sc high (first serial clock after real time transfer) 8810ns t tch trg hold time to ce high 8 8 10 ns t trh trg hold to re high 8 8 10 ns t trp re high to sc high (serial write transfer) 15 15 20 ns t tsl sc high delay to trg high during a real time read transfer 555ns 1. measured with the specified current and 30 pf load for the serial port. output referenced levels: v oh = 2.0v and v ol = 0.8v.
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 65 fast page (fp) read cycle t rc t rp t ras t rcd t rsh t cas t csh t asr t rah t rad t asc t cah t su(sfr) t h(sfr) t oes t rcs t rch t cac t oea t rac t aa t off re ce a 0 -a 8 dsf trg w dq t su(sfc) t h(sfc) t tls t tlh row valid data out hi - z hi - z : h or l column t ral t rrh
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 65 33g0307 sa14-4751-05 revised 3/98 fast page read operation t rp t ras t cas t cp t rsh t asr t rah t asc t rad t cah t ar t su(sfr) t h(sfr) t su(sfc) t tls t tlh t rcs t rch t oea t aa t cac t off t acp t off re ce a 0 -a 8 dsf trg w dq row column a column b data a data b hi - z t rc hi - z : h or l
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 65 edo page read cycle t rp t crp t rcd t cas t rsh t asr t rah t rad t asc t cah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t rcs t rch t rrh t cac t oea t rac t oez re ce a 0 -a 8 dsf trg w dq t ras t csh row column valid data out : h or l t rc hi - z
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 65 33g0307 sa14-4751-05 revised 3/98 edo page read operation t rp t ras t cp t cas t rsh t asr t rah t asc t rad t cah t ar t su(sfr) t h(sfr) t su(sfc) t tls t tlh t rcs t rch t oea t cac t rac t aa t acp t oez re ce a 0 -a 8 dsf trg w dq row column a column b hi - z data out a t rc t rcd data out b : h or l
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 65 write cycle (early write) t wc t rp t ras t crp t rcd t rsh t csh t cas t asr t rah t rad t asc t cah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t wsr t rwh t wcs t wp t wch t wcr t ms t mh t dsc t dh t dhr re ce a 0 -a 8 dsf trg w dq row column wpb mask valid data in : h or l
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 65 33g0307 sa14-4751-05 revised 3/98 fast page mode (early write ) t rp t ras t rcd t cp t cas t asr t rah t asc t rad t cah t su(sfr) t h(sfr) t su(sfc) t tls t tlh t wsr t rwh t cwl t wcs t wch t ms t mh t dsc t dh re ce a 0 -a 8 dsf trg w dq row column a column b wpb mask data in a data in b t wc : h or l t h(sfc)
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 65 write cycle (late write) t wc t rp t ras t rcd t rsh t cwl t cas t asr t rah t asc t cah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t wp t ms t mh t dsw t dh re ce a 0 -a 8 dsf trg w dq row column mask valid data in t ar t oez t oeh t rwl : h or l t ghd
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 65 33g0307 sa14-4751-05 revised 3/98 read-modify-write cycle t rwc t rp t ras t cas t asr t rah t asc t cah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t wsr t rwh t rcs t oeh t cwl t rwl t wp t ms t mh t oea t cac t aa t rac t oez t ghd t dh re ce a 0 -a 8 dsf trg w dq row wpb mask data out data in : h or l t dsw column
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 65 skewed ce (overlapping ce) edo read operation t rp t ras t cas t asr t rah t asc t rad t cah t su(sfr) t h(sfr) t su(sfc) t tls t tlh t rcs t rch re uce a 0 -a 8 dsf trg we row t rc t rcd : h or l lce column t cas t clch t oez t aa t rac t cac valid data out valid data out hi - z hi - z dq 0 -dq 7 dq 8 -dq 15
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 65 33g0307 sa14-4751-05 revised 3/98 skewed ce (non-overlapping ce) edo read operation t rp t ras t cas t asr t rah t asc t rad t su(sfr) t h(sfr) t su(sfc) t tls t tlh t rcs t rch re uce a 0 -a 8 dsf trg we row t rc t rcd : h or l lce t cas t chcl t oez t cac t aa t rac data out data out hi - z hi - z t rsh t cah column b t asc t cah t oea t aa column a t cac dq 0 -dq 7 dq 8 -dq 15 t h(sfc)
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 65 2 ce byte write operation ( ce overlapping) t dsc t dh valid data in t rp t ras t cas t asr t rah t asc t rad t cah t su(sfr) t h(sfr) t su(sfc) t tls t tlh t wcs re uce a 0 -a 8 dsf trg we row t wc : h or l lce column t cas t clch t wch t cwl t dsc t dh valid data in dq 0 -dq 7 dq 8 -dq 15 t h(sfc)
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 65 33g0307 sa14-4751-05 revised 3/98 skewed w operation t asc t cah t dsw t dh t rp t ras t asr t rah t rad t su(sfr) t h(sfr) t su(sfc) t tls t tlh t wcs re a 0 -a 8 dsf trg lwe row t wc ce column t cas t wch t cwl t dsc t dh data in dq 0 -dq 7 dq 8 -dq 15 data in t h(sfc) t wp uwe t rwl t rcd : h or l
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 29 of 65 load color register cycle (early load) t rp t ras t rc t rcd t cas t asr t rah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t wsr t rwh t wcs t wch t wcr t dsc t dhr t dh re ce a 0 -a 8 dsf trg w dq refresh row color data : h or l
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 30 of 65 33g0307 sa14-4751-05 revised 3/98 load color register cycle (late load) t rp t ras t rc t rwl t rcd t cas t cwl t asr t rah t su(sfr) t h(sfr) t su(sfc) t h(sfc) t tls t tlh t wch t wsr t rwh t oeh t wp t dsw t ghd t oez t dhr t wcr t dh re ce a 0 -a 8 dsf trg w dq refresh row color data : h or l
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 31 of 65 load mask register (early load) t rp t ras t rc t rcd t cas t asr t rah t su(sfr) t h(sfr) t tls t tlh t wsr t rwh t dsc t dhr t dh re ce a 0 -a 8 dsf trg w dq t su(sfc) t h(sfc) refresh row mask register data t wcs t wch : h or l
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 32 of 65 33g0307 sa14-4751-05 revised 3/98 load mask register (late load) t rp t ras t rc t rwl t rcd t cas t cwl t asr t rah t su(sfr) t h(sfr) t tls t tlh t wcr t wch t wsr t rwh t oeh t wp t dsw t dhr t dh re ce a 0 -a 8 dsf trg w dq t su(sfc) t h(sfc) refresh row mask register data : h or l t ghd
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 33 of 65 block write (no mask) operation (early write) t wc t rp t ras t rcd t cas t cp t asc t cah t asc t rad t cah t ar t su(sfr) t h(sfr) t tls t tlh t wsr t rwh t wcs t wch t dsc t dh re ce a 0 -a 8 dsf trg w dq row block a block b ignore a 0 - a 2 ignore a 0 - a 2 column mask for block a column mask for block b no mask (non-persistent or persistent) applied to block write cycles. : h or l start address start address t su(sfc) t h(sfc)
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 34 of 65 33g0307 sa14-4751-05 revised 3/98 non-persistent mask block write operation (early write) t wc t rp t ras t rcd t cas t cp t rsh t cas t asc t cah t asc t rad t cah t ar t su(sfr) t h(sfr) t tls t tlh t wsr t rwh t wcs t wch t ms t mh t dsc t dh t dhr re ce a 0 -a 8 dsf trg w dq row block a non-persistent mask block write operation. column mask for a column mask for b wpbm this assumes that load mask register cycles has not been initiated prior to : h or l start address block b start address t su(sfc) t h(sfc)
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 35 of 65 persistent mask block write operation (early write) t wc t rp t ras t rcd t cas t cp t rsh t cas t asc t cah t ar t su(sfr) t h(sfr) t tls t tlh t wsr t rwh t wcs t wch t dsc t dh re ce a 0 -a 8 dsf trg w dq lmr cycle has been invoked prior to block write operation. mask from mask register is applied to the color register data during block write cycles. column mask for block a column mask for block b : h or l block a start address block b start address a 2 - a 0 dont care a 2 - a 0 dont care t su(sfc) t h(sfc)
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 36 of 65 33g0307 sa14-4751-05 revised 3/98 flash write cycle t rp t wc t ras t crp t chr t asr t rah t su(sfr) t h(sfr) t tls t tlh t wsr t rwh t ms t mh re ce a 0 -a 8 dsf trg w dq wpb mask : h or l row address
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 37 of 65 re only refresh (ror) 1 t rp t rc t ras t crp t asr t rah t tls t tlh t wsr t rwh re ce a 0 -a 8 trg w dsf t h(sfr) t su(sfr) row address 2 status at re fall w(1) dsf (2) operation x hx see state table see state table : h or l ror h
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 38 of 65 33g0307 sa14-4751-05 revised 3/98 ce before re refresh (cbr-with mode reset) t rp t ras t rc t rpc t chr t csr t wsr t rwh t su(sfr) t h(sfr) : h or l re ce w dsf
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 39 of 65 ce before re refresh (cbrn-no mode reset) t rp t ras t rpc t csr t chr t wsr t rwh t su(sfr) t h(sfr) re ce w dsf t rc : h or l
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 40 of 65 33g0307 sa14-4751-05 revised 3/98 ce before re refresh (cbrs) cycle with stop register set t rp t rc t ras t rpc t csr t chr t asr t rah t su(sfr) t h(sfr) t wsr t rwh re ce a 0 -a 8 dsf w stop address serial port : h or l
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 41 of 65 ram ----> sam (full register read transfer) t sca t soh t cas t asc t cah t tch t trh t dth t tsl t sc t scp t sws t csd t rsd t sca t sez t sea re ce a 0 -a 8 dsf w trg sc sdq se t asr t rah t su(sfr) t h(sfr) t wsr t rwh t tls t tlh t ras t rp t rc row address which half of row to transfer a 8 , a 7 - a 0 start address for serial port read new data new data old data old data t sca : h or l hi - z
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 42 of 65 33g0307 sa14-4751-05 revised 3/98 ram---->sam (real time) full register read transfer re ce a 0 -a 8 dsf w trg sc sdq se t rp t rc t ras t rcd t cas t asr t rah t asr t rah t su(sfr) t h(sfr) t wsr t rwh t tls t cth t dth t sc t rth t rsd t sws t csd t sca t soh row ca 0 - ca 7 , ca 8 serial port which half of row old data old data old data old data old data new data new data data out from real time transfer requires precise synchronization of sc clock with memory clock t sca t sca t scc t tch t trh location 256 : h or l start address to be transferred
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 43 of 65 split register read transfer t rc t rp t ras t cas t asr t rah t asc t cah t su(sfr) t h(sfr) t wsr t rwh t tls t tlh t d(tprl) t d(rhms) t sca re ce a 0 -a 8 dsf w trg sc sdq se a minimum delay of t d(tprl) to avoid contention. note that the transfer can wait in split-register transfer operations. dont rush to start a transfer. caution: row ca 8 , a 6 -a 0 tap n ca 7 is dont care ca 8 determines which part of the row to transfer bit 127 or 255 tap point m bit bit 255 or 127 never start a transfer at the same time the last bit from a particular half of sam is being read. allow 1) been completed ahead of time by a minimum time of t d(rhms) before the sc clock reads the last bit out of the 2) never wait too long to start a transfer to the particular half of sam. the transfer cycle must have particular half of sam never wait till the last moment to initiate a split-register transfer. low : h or l t sca t sca tap point m tap point n t rsd
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 44 of 65 33g0307 sa14-4751-05 revised 3/98 full register write transfer t rp t wc t ras t cas t asr t rah t asc t cah t su(sfr) t h(sfr) t wsr t rwh t ms t mh t tls t tlh t srs t trp t rsd t csd t sds t scp t sfd re ce a 0 -a 8 dsf w dq trg sc sdq se row a 8 , a 7 -a 0 wpb mask old data in new data write new data write old data transferred to row [r 8 - r 0 ] based on ca 8 optional low allow suf?cient time, at least t srs (min) for the completion of the allow suf?cient time, at least t trp (min) for the transfer to be completed before starting a write. 1) write of previous data before initiating a transfer. 2) : h or l t sdh t sdh t sds
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 45 of 65 split register write transfer caution: t wc t rp t ras t cas t asr t rah t asc t cah t su(sfr) t h(sfr) t wsr t rwh t ms t mh t srs t trp t sds t sdh t sds t sdh re ce a 0 -a 8 dsf w dq sc sdq se row a 8 , a 6 - a 0 ca 7 is dont care wpb mask last bit of old data 255 or 127 last bit of old data 127 or 255 new data new data write starting at other half of sam 1) it is not a good idea to rush to start a split write transfer especially when you have all the time on earth to initiate a split transfer. 2) allow a delay of t srs (min) to initiate a transfer from the time of writing the last bit [255 or 127] in the serial port. allow at least t trp (min) for the completion of a transfer cycle before start initiating the new data write. you can start a transfer from the particular half of sam after few cycles of write in the other half of sam. dont wait till the last moment. tap[a 6 - a 0 ] in the low old data data in : h or l
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 46 of 65 33g0307 sa14-4751-05 revised 3/98 functional description the dram array is organized as 512 rows x 512 columns x 16 bit wide. the device is capable of performing normal read/write operations similar to a dram. besides fast page read/write, the 4-mb vram has the fol- lowing added functions: ? full register read transfer ? split register read transfer ? full register write transfer ? split register write transfer ? 8 column block write ? full row flash write ? extended data out (edo) ? serial port read ? serial port write power up or vram initialize process after v cc has reached its regulated value, allow at least 100 m s for build up of n-well voltage inside the chip. perform at least 8 cas-before- ras (cbr) refresh cycles to reset unwanted mode(s) which may be set dur- ing power up. for more details refer to the application note, designing with 4-mb vram. the serial port will be initialized with the jump address of 128 bit at power up, thereby requiring no stop address setting by the user for split read or split write in normal mode operations . dram refresh operation dram array consists of volatile cells, therefore these cells need to be refreshed periodically. the minimum rate for vram is 512 refresh cycles every 32ms. every cell therefore gets a chance to be refreshed every 32 ms. the sam registers memory is static in nature and therefore requires no refresh. the following refresh modes are available in ibm's 4-mb vram: re only refresh (ror) a cycle having only re active refreshes all cells in one row of the storage array. a high ce is maintained while re is active to keep dqs in high impedance. note that the row address for refresh is supplied by the user. re only refresh mode will not clear any unknown modes at power up. therefore, cbr cycles at power up must be performed to clear any unknown modes . the timing diagram on page 37 shows a re only refresh mode. ce before re refresh (cbr) the cbr refresh mode is selected by bringing the ce low before re is brought low and keeping dsf low as shown in the timing diagram on page 38. an internal address counter selects the row to be refreshed. cbr cycle will reset any special modes set by cbrs or any persistent mask . note that dqs are in high-z state during cbr cycle. ce before re refresh without mode reset (cbrn) cbrn mode is set by bringing ce low before re is brought low and keeping w and dsf high at the falling edge of re. the internal counter selects the row to be refreshed . cbrn will neither clear any special modes set by the cbrs cycle nor any masks .
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 47 of 65 ce before re refresh with stop register set (cbrs) the cbrs operation is selected by bringing w and ce low before re is brought low and keeping dsf high as shown in the timing diagram on page 40. an internal address counter selects the row to be refreshed. this cycle is also used to set the chip into serial register stop mode (srs). full compatibility is provided between half depth sam and full depth sam by performing split transfer in srs mode using stop address of 127 or less. for more details, refer to application note, half sam and full sam compatibility. recommended cbr, cbrs, and cbrn cycles to ensure that the device has not entered unwanted register modes at power up, at least eight cbr cycles must be executed before normal operation of the device is resumed . a cbr after each vertical retrace is recommended. this fail-safe routine is for cases where a system misoperation causes entry into an unwanted mode. if the stop register function is used, then a cbrs must be invoked following every cbr cycle. if the stop register function is not required and persistent write masking is employed, then use a cbrn. cbrn does not clear the old mask. byte control the 4-mb vram is available with either dual w or dual ce. a dual ce part has lower and upper byte control. the lce controls the dq 0 -dq 7 while uce controls dq 8 - dq 15 . individual byte control can be applied during read and write operations on the primary port. a dual w part has a lower and upper w. the lw and uw allow individual byte control of the dqs during write operations. the lw controls dq 0 -dq 7 and uw controls dq 8 - dq 15 . individual byte control can be applied to the dram read, write, block write, load mask register and load color register cycles. read cycle a read cycle is executed by activating re, ce, and trg and by maintaining w high while ce is active. the dqs remain in high-z until valid data appears at the output at access time. device access time, t acc , will be the longest of the four calculated intervals: ?t rac access time from re falling edge ?t rcd ( re to ce delay) + t cac (access time from ce falling edge) ?t rad ( re to column address delay) + t aa (access time from column address) ? re to trg delay + t oea (access time from trg) device dependent parameters are: t rac , t cac , t aa and t oea . system dependent parameters are: t rcd , t rad and re to trg delay. output becomes valid after the access time has elapsed. it remains valid while ce and trg are low (fast page parts only). it remains valid while trg is low (edo parts only). either ce or trg high returns the output pins to high-z (fast page parts only). trg high returns the output pins to high-z (edo parts only). write cycle a write cycle is executed by bringing w low during re/ ce cycle. the falling edge of ce or w whichever occurs later strobes the data on dq pins into the on-chip data latch.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 48 of 65 33g0307 sa14-4751-05 revised 3/98 early write cycle an early write cycle is executed by bringing w low before ce falls. data is strobed by ce with setup and hold times referenced to this signal. this is the mode that is generally used for graphics applications. trg can be in any state while w is active. late write cycle a late write is executed by bringing w low after ce goes low. the input data is strobed by w with setup and hold times referenced to w signal. the late write cycle is used for read-modify-write operations. write-per-bit mask (wpbm) cycle a write-per-bit mask cycle uses an i/o mask function to allow the system designer the flexibility of writing or not writing any combinations of dq 0 through dq 15 . two types of masking are possible: 1. non-persistent mask or new mask this mask has to be loaded at each re fall time as shown in the timing diagram on page 34. w must be low as re falls. the dqs latched at re fall time are used as mask bits for write cycle(s) for the particular re cycle. if mask bit is 1, the corresponding dq input bit is written. if mask bit is 0, the corresponding dq input is not written. 2. persistent mask or old mask if a load mask register cycle has been performed and has not been cleared by a cbr refresh cycle prior to a write cycle, and w is low at re fall time, data at dq pins at re fall time will be ignored and the data from mask register is applied to the following: a. dq inputs during write cycles if w is low at re fall time. b. color register data during block write and flash write cycles if w is low at re fall time . read-write/read-modify-write cycle a read-modify-write is performed by first performing a normal read, then tri-stating the dq pins with trg, placing data to be written on the dq pins, and then executing a write operation. a wpbm can be loaded at the falling edge of re. the input data is strobed in reference to w. this operation is illustrated in the timing diagram on page 24. load mask register cycle in this cycle, data on dq pins is written to a 16-bit write mask register, where it is retained and used by sub- sequent masked write and masked block write cycles. this mask can be cleared by executing cbr cycle or by turning the power off. the mask data in the mask register can be changed by issuing another load mask register cycle. load color register cycle the load color register cycle is used to load the 16 bit color register, where it is retained to be used for data during block write and flash write operations.
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 49 of 65 block write operation the block write cycles are useful for clearing windows and for accelerating polygon fill operations. in all block write operations, the data is always supplied by the color register which is loaded by invoking a load color register operation prior to the block write cycle(s). the color register data bits can individually be masked by either loading the mask at re fall time (non-persistent mask) provided that no load mask regis- ter operation has been performed prior to invoking block write cycle(s). if a load mask register operation has been performed and w is low at re fall time, wpbm mask at re time will be ignored and the mask from the mask register (persistent mask) will be applied to the color data bits during block write cycle(s). lower or upper or both bytes can be written during block write cycle(s) . also a feature known as individual col- umn masking can be used to mask all or any of the 8 columns by loading the column mask at dq pins at ce fall time. this operation is illustrated in and the application note, 8 column block write. for example, if dq 0 is 0, mask the lower byte of column 1 in the block. if dq 8 is 1, write in the upper byte of column 1 1l = lower byte of column 1. 1u = upper byte of column 1. block write (no mask) the data from the color register is written to any or all of the eight columns starting with the column address a 8 -a 3 (a 2 , a 1 , a 0 are don't care). any column or columns in a block of 8 columns can be masked by latching the dq data at ce fall time during block write page cycles in a way as illustrated in the timing diagram on page 33. both w should be kept high at re fall time so that no mask is used at block write cycle time . block write (non-persistent mask) the wpbm is loaded by bringing w low at re fall time and latching the data present at dq pins. this mask is applied to the data from color register during block write page cycles. note that the masked data is written to all or any of the non-masked columns in the selected block. the wpbm so latched at re fall time is appli- cable during that particular re active cycle time only. block write (persistent mask or old mask) an lmr cycle is initiated to load the mask register prior to executing a block write operation with persistent mask. the 16-bit mask register supplies the bit mask for color register data during page mode block write cycles. this masked data is then written to all or any of the non-masked columns in the 8-column block. w is low at re time and any data on dq pins at re fall time will be ignored. to clear the persistent mask, a cbr cycle is initiated . dq data at ce fall time during block write cycle(s) dq i = 0, mask the selected column in the block dq i = 1, write the data in the selected column in the block dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 1l 2l 3l 4l 5l 6l 7l 8l 1u 2u 3u 4u 5u 6u 7u 8u
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 50 of 65 33g0307 sa14-4751-05 revised 3/98 flash write the flash write operation causes an entire row (512 x 16 bits) of data to be written with the contents of the color register. the color register must be loaded on a previous load color register (lcr) cycle. the flash write operation can be without mask, with new mask wpbm or old mask wpbm as explained in mask write operations. the only difference is that the mask is applied for the data in the whole row. note that there is no provision for individual byte control, therefore both the bytes will be written or masked . fast page cycle operation fast page mode cycles allow faster memory access by using the same row address while successive column addresses are strobed onto the chip. the re signal is kept low while successive ce cycles are executed. the data rate is faster because row addresses are maintained internally and do not have to be reapplied. in fast page mode operation, read, write, read-modify-write cycles may be executed. during a fast-page read cycle, the dq pins stay in high-z until valid data appears at the output pins at access time. the access time in this cycle will be the longest of the following intervals. t acp = access time from start of column precharge t cp + t t + t cac = column precharge time + transition time + access time from ce fall time = ce high to column address delay + t aa extended data out (edo) i n extended data out mode, the primary port output drivers are not turned off by the rising edge of ce . as rising edge of ce does not turn off the data, the resulting longer data valid time allows speedup of the fast page cycle time. fast page mode applications that try to run at minimum cycle times find that timing skews and propagation delays make the data valid time so narrow that reliable sampling is impossi- ble. edo solves this problem by providing longer data valid time. the device access time is the longest of the following intervals: ? t acp ? t aa ? t cac the detailed explanation of edo and fast page is given in the application note, edo for higher bandwidth. serial port operation the serial port is always in either read or write mode. to switch the serial port from read to write or vice versa, a transfer operation of the appropriate type must be executed. a read transfer operation will put the serial port into read mode if it is not already in read mode. a write transfer will switch the serial port into write mode if it is not already in write mode. to prevent storing of the current contents of the sam when first switching to write mode, a write transfer operation with the wpbm set to block all 16 bits should be performed . when se is low, each serial clock will cause a read/write of the sam location addressed by the internal serial port address counter. when se is high, the serial port is disabled for read/write, and the sdqs are in high-z state. note that each sc clock causes the internal address counter to increment independent of the state of se .
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 51 of 65 transfer modes the following transfer modes are available: 1. full read transfer (normal) mode. 2. split read transfer (normal) mode. 3. full read transfer (srs) mode. 4. split read transfer (srs) mode. 5. full write transfer (normal) mode. 6. split write transfer (normal) mode. 7. full write transfer (srs) mode. 8. split write transfer (srs) mode. full register read transfer (normal) mode the full register read transfer operation is illustrated in the timing diagram on page 41. this operation will load the entire sam (256 x16 bits) from the selected segment of the row. ca 8 controls which half of the selected row needs to be transferred. if ca 8 at ce fall time is 0, the lower half of the selected row is trans- ferred. if ca 8 at ce fall time is 1, the upper half of the selected row is transferred. ca 7 -ca 0 address sup- plied by the user at ce fall time is used to provide the starting address for reading of data from the serial port. the sam has 256 locations to be addressed starting from 0 to 255. during the full read transfer cycle the start address register as well as the serial port counter will be loaded, with the user supplied address ca 7 - ca 0 . ca 7 equals 0 is associated with the lower half of the sam and ca 7 equals 1 is associated with the upper half of the sam. a full register read transfer from the selected row to sam is shown in the timing diagram on page 51. the example shows a transfer based on user supplied ca 8 equals 1. the serial port counter is set to the address ca 7 -ca 0 specified by the user at ce fall time during the full read transfer cycle. the next sc cycle following the transfer will start reading data from this point in the sam. reading will continue until the end of the sam location 256 and will wrap around. to keep serial data out continuous, either a split read transfer or a full read transfer must be executed as the sam runs out of new data. see the timing diagrams for the necessary timing requirements for either method of loading the sam full register read transfer (normal) mode array 511 0 383 511 rows cols sam 0 127 128 255 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 52 of 65 33g0307 sa14-4751-05 revised 3/98 split register read transfer (normal) mode the split read transfer is used to read data continuously from the serial port without having to worry about synchronizing the sc clock with the operation of the primary port. this transfer operation loads 128 x16 bits of a wordline into half of the sam. the user supplied column address bit ca 8 and an internally generated ca 7 determines which quarter of the word line is transferred to the sam. note the user supplied ca 7 at ce fall time during transfer cycle is a don't care and is internally generated based on which half of the sam is active. this way, the inactive half of sam can be loaded with the new data while data is being read out of the other active half. the start address is given by ca 6 - ca 0 but is held in a tap address pointer register until the serial counter reaches the jump address (127/255). at that point, the start address register is loaded with the address from the tap address register. the serial port counter will also be loaded with this address at the same time. the reading of data will start from this address in the other half of sam that was previously inactive at the next sc clock. the split read transfer in normal mode is illus- trated in the timing diagram on page 43. the example in the timing diagram on page 53 illustrates a split read transfer between dram and sam based on user supplied ca 8 during split read transfer cycle and an internally generated ca 7 . in the first example (ca 8 = 1), the serial port is active reading data from the upper half of the sam while the lower half of sam is idling. therefore, ca 7 is internally changed to 0 and the transfer is forced to lower half of sam. in the second example, the serial port is active reading data from the lower half of sam, the transfer is therefore forced to the upper half of sam. note: there must be a full read transfer prior to any split read transfer. after the full read trans- fer, any number of split read transfers can be performed. the split read transfer can be initiated to the idling part of sam at any time while the active half is being read. it is generally a good practice to perform a split read transfer to the idle half of sam at any time way ahead of the last data being read out of the active half of sam .
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 53 of 65 split register read transfer (normal) mode array 511 rows cols sam 0 127 128 255 array 511 rows cols sam 0 127 128 255 sp sp 0 383 511 255 127 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 54 of 65 33g0307 sa14-4751-05 revised 3/98 full register write transfer (normal) mode the full write transfer operation is illustrated in the timing diagram on page 44. this operation will store the contents of the sam at the address specified by row address (ra 8 - ra 0 ) and ca 8 . ca 8 controls the transfer of data to the particular half of the row. if ca 8 at ce fall time is 0, the data from sam is stored in the lower half of the row. if ca 8 at ce fall time is 1, the upper half of the selected row is loaded. ca 7 -ca 0 address supplied by the user at ce fall time in a transfer cycle is used to provide the start- ing location for writing the data in the serial port on the next sc clock following the transfer. during the full write transfer cycle, a wpbm can be loaded at re fall time to mask the selected data bits at transfer time. generally, it is a good practice to mask all the data bits at the first full write transfer cycle to prevent transferring of old data left over from previous read transfer operations. a full register write transfer from sam to dram is shown in the timing diagram on page 54. the example shows a transfer based on user supplied ca 8 equals 1. the serial port counter is set to the address ca 7 - ca 0 specified by the user at ce fall time during the full register write transfer cycle. the next sc clock fol- lowing the transfer will start writing data from this point in the sam. full register write transfer (normal) mode rows cols array 511 sam 0 127 128 255 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 55 of 65 split register write transfer (normal) mode the split write transfer is used to write data continuously in the serial port without having to worry about synchronizing the sc clock with the operation of the primary port. this transfer operation stores 128x16 bits from sam in the selected row segment. ca 8 at ce fall time during a split write transfer cycle determines to which half of the row the data from sam is going to be stored. ca 7 is a don't care and is internally gener- ated based on which half of the sam is active . this way, the data from the idle part of sam can be trans- ferred to the selected row in dram while the new data is being written in the active half of sam. the start address is given by ca 6 -ca 0 but is held in the tap address register until the serial port counter reaches the jump address. at that point, the start address register is loaded with the address from the tap address regis- ter and the serial port counter will also be loaded with this address at the same time. the writing of data in the previous inactive half of sam will start at this address at the next sc clock. the split write transfer in normal mode is illustrated in the timing diagram on page 45. the example in the timing diagram on page 56 illustrates a split write transfer between sam and dram based on user supplied address ca 8 at ce fall during transfer cycle and an internally generated ca 7 . in the first example, the serial port is active writing data in the upper half of the sam while the lower half of sam is idling. therefore, ca 7 is internally changed to 0 and the transfer is forced to lower quarter of the upper half of the selected row based on ca 8 = 1. in the second example, user supplies bit ca 8 is 1 and the serial port is active writing data in the lower half of sam, the transfer is therefore forced to the uppermost quarter of the selected row. note: a full write transfer with wpbm must be performed before the start of any split write trans- fer. after the full write transfer, any number of split write transfers can be performed. the split write transfer can be initiated from the idling part of sam at any time while the active half is being written. it is generally a good practice to perform a split write transfer from the idle half of the sam at any time which is way ahead of the last data being written into the active half of the sam.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 56 of 65 33g0307 sa14-4751-05 revised 3/98 split register write transfer (normal) mode array 511 rows cols sam 0 127 128 255 array 511 rows cols sam 0 127 128 255 sp sp 0 383 511 255 127 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 57 of 65 serial register stop (srs) mode the srs mode is very useful in applications where the dram data is arranged in the form of tiles and the serial port is read out in scan line order. a typical case is that of vectors that cross many scan lines on the screen. the pixels for vector(s) can be written in a single row or minimum number of rows depending on the tile width using page mode cycles. a detailed explanation is given in the application note, read/write trans- fer operation. the srs mode is set by executing cbrs cycle just after power up. the 4-mb vram has an 8-bit stop register. the stop register value is latched at the falling edge of re during cbrs cycle using address inputs a 4 -a 7 (a 0 -a 3 and a 8 are don't care). up to eight different stop positions or boundaries can be specified for each half of sam as shown in the stop register set table on page 57 by invoking a cbrs cycle. note: if the serial port counter is between 128 and 255, the stop address is equal to 128 plus the number(s) specified in column 3 of the stop register set table on page 57. when the counter reaches the stop address, the counter is loaded with the tap point register address that was saved during the split transfer cycle . for more details of the stop column control for the serial port, refer to the application note, read/write transfer operation. another application of srs mode is to make half depth sam vram part compatible to full depth sam vram parts. full compatibility is provided between half depth sam and full depth sam by performing split transfer in srs mode using stop address of 127 or less. for more details, refer to applica- tion note, half sam and full sam compatibility. full register read transfer (srs) mode a full read transfer in srs mode will transfer 256 x16 bits from the selected row based on ca 7 at ce fall time during the full read transfer cycle. ca 8 is a don't care. if ca 7 is 0, data from locations in the selected row having physical address ca 7 equal to 0 is transferred to sam. if ca 7 is 1, data from locations that have a physical address ca 7 equal to 1 is transferred to sam. note that the data corresponding to physical address ca 8 equal to 0 is associated with the lower half of sam while the data corresponding to physical address ca 8 equal to 1" in a row is associated with the upper half of sam. the timing diagram on page 58 illustrates a full read transfer in srs mode between dram and sam. stop register set address by user a 8 - a 0 stop register value: a 7 - a 0 if the serial port counter is less than 128, the stop address is equal to whichever occurs first x 1111 xxxx x 0111 xxxx x 0011 xxxx x 0001 xxxx 0111 1111 0011 1111 0001 1111 0000 1111 127 63,127 31,63,95,127 15,31,47,63,79,95,111,127
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 58 of 65 33g0307 sa14-4751-05 revised 3/98 the example illustrates a full transfer in srs mode based on ca 7 =1. split register read transfer (srs) mode the split read transfer in srs mode is used to read data continuously from the serial port without synchro- nizing the sc clock with the operation of the primary port. this mode is most useful for tiling applications. it is also used to make half depth sam vram parts compatible to full depth sam vram parts. when the split read transfer in srs mode is invoked, 128 x16 bits are transferred from a selected row based on user sup- plied column address ca 7 at ce fall time and the serial port counter reading. for example if the upper half of sam is being read and user supplied ca 7 is 1, then the data having physical addresses ca 7 =1 and ca 8 = 0" from the selected row is transferred to the lower half of sam. if the lower half of sam is being read and the user supplied column address ca 7 is 1, the data having physical addresses ca 7 = 1 and ca 8 =1 from the selected row is transferred to the upper half of sam. this is illustrated in the timing diagram on page 59. the user supplied column address ca 6 - ca 0 is held in a tap address register until the serial port counter reaches the stop address. at that point, the start address register is loaded with the contents of the tap address register. the serial port counter is updated with this address at the same time. the reading of data from the serial port will commence from this address in the previously inactive half of sam at the next sc clock. full register read transfer (srs) mode array 511 rows cols sam 0 127 128 255 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 59 of 65 split register read transfer (srs) mode array 511 rows cols sam 0 127 128 255 array 511 rows cols sam 0 127 128 255 sp sp 0 383 511 255 127 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 60 of 65 33g0307 sa14-4751-05 revised 3/98 write transfer (srs) modes full register write transfer (srs) mode the full register write transfer operation in srs mode is illustrated in the timing diagram on page 60. this operation will store the entire contents of the sam in the row specified by row address (ra 8 - ra 0 ) at re fall time and ca 7 at ce fall time during the full register write transfer cycle in srs mode. ca 7 controls the transfer of data to the particular segments of the row. if ca 7 at ce fall time during a full register transfer cycle is 1, the data from sam is stored in those segments of the row whose physical address bit ca 7 equals to 1. data from the lower half of sam is transferred to locations in the row that have physical address ca 8 equal to 0, data from the upper half of sam is transferred to locations in the row that have physical address ca 8 equal to 1. ca 7 -ca 0 address supplied by the user at ce fall time is loaded in the start address register to be used as starting location for writing the data in the serial port on the next sc clock following the transfer. during the full register write transfer cycle, a wpbm can be loaded at re fall time to mask the selected data bits at transfer time. generally, it is a good practice to mask all the data bits at the first full register write transfer cycle to prevent writing of old data left over from previous read transfer operations. the example illustrates a full transfer in srs mode based on ca 7 =1. full register write transfer (srs) mode array 511 rows cols sam 0 127 128 255 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 61 of 65 split register write transfer (srs) mode the split register write transfer is used to write data continuously in the serial port. this transfer operation stores 128 x16 bits from sam to the selected segment in a row specified by (ra 8 -ra 0 ) at re fall time and ca 7 at ce fall time during the transfer cycle.the serial port counter reading at the time of transfer determines the location of the segment in the selected row for the data transfer. the split register write transfer in srs mode is illustrated in the timing diagram on page 62. the first example illustrates a split register write trans- fer between sam and dram based on ca 7 and the status of which half of sam is active and which half is inactive. in the example, user supplied address bit ca 7 is 1 and the upper half of sam is active (data being written in that half) while the lower half of sam is idling. therefore, data from the lower half of sam is forced to the upper quarter of the lower half of the selected row. note that the data in the lower half of sam is associated with row locations that have physical address bit ca 8 equal to 0, while the data in the upper half of sam is associated with the row locations that have physical address bit ca 8 equal to 1 . the user supplied address bits ca 6 - ca 0 are stored in the tap address register during the transfer cycle. when the serial port counter reaches the stop address, the start address is loaded with the contents of tap address register. at the same time, the serial port counter is updated with the new start address. the writing of data in the previously inactive half of sam will start from this new start address at the next sc clock.
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 62 of 65 33g0307 sa14-4751-05 revised 3/98 split register write transfer (srs) mode array 511 rows cols sam 0 127 128 255 array 511 rows cols sam 0 127 128 255 sp sp 0 383 511 255 127 0 383 511 255 127 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1 ca 7 =0 ca 8 =0 ca 7 =1 ca 8 =0 ca 7 =0 ca 8 =1 ca 7 =1 ca 8 =1
ibm025160 ibm025170 IBM025161 ibm025171 256k x 16 multiport video ram 33g0307 sa14-4751-05 revised 3/98 ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 63 of 65 package diagram dwg. ssog (dimensions in millimeters) 2.38 0 -5 typ detail b 14.00 - 14.50 11.90 - 12.10 pin #1 identi?er 26.17 - 26.43 0.05 - 0.25 0.25 basic gaugeplane 0.48 - 0.68 detail b 0.325 0.65 detail c scale 30/1 0.325 seating plane c 0.30 - 0.45 0.8 basic max
ibm025170 ibm025160 ibm025171 IBM025161 256k x 16 multiport video ram ?ibm corporation, 1995. all rights reserved. use is further subject to the provisions at the end of this document. page 64 of 65 33g0307 sa14-4751-05 revised 3/98 revision log rev contents of modi?cation 12/93 1. new mechanical drawings. 2. description on how ibms half depth sam is compatible to a full depth sam. 3. another pin configuration diagram in the section title module pin definitions. 2/94 1. added note to ordering information section. 2. remove t trg parameter from timing table and read cycle timing. 3. in extended data out diagram, the w is changed from high to dont care at re fall. 4. changed dc currents for 5.0 v and 3.3 v. 5. change ssog size from .500 to .472" in pin configuration and module pin definition. 9/94 updated and added timing notes. 4/95 major revision to update to die revision d preliminary specifications. 10/95 die rev d specifications and update of timing diagrams. 3/98 deleted qsf part numbers.
intern ational business machines corp.1998 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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